JEDEC
Stress-test-driven qualification of integrated circuits
The JEDEC baseline for qualifying a commercial or industrial IC: which stress tests to run, on how many parts from how many lots, and what counts as a pass. The tests themselves are defined in JESD22.
Official source JEDEC JESD47↗
On the map Burn-In, Failure Analysis
See also JESD22 test methods, AEC-Q100
JEDEC
The family of reliability test methods. The ones every qualification plan contains: A108 high-temperature operating life (HTOL), A104 temperature cycling, A110 highly accelerated stress test (HAST), A101 temperature-humidity-bias (THB), A103 high-temperature storage, and A113 preconditioning to simulate board assembly before the rest.
In practice. An Indian reliability lab earns its keep by running these to JEDEC conditions with NABL-accredited scope, so customers do not ship samples overseas for qualification.
Also written as HTOL, HAST, THB, temperature cycling, TC, preconditioning, JESD22-A104, JESD22-A110, JESD22-A108
Official source JEDEC JESD22-A108 (HTOL)↗ · JEDEC JESD22-A104 (temperature cycling)↗ · JEDEC JESD22-A110 (HAST)↗
On the map Burn-In, Failure Analysis, Qualification
See also JESD47, J-STD-020 and MSL, ISO/IEC 17025
IPC/JEDEC
Moisture/reflow sensitivity classification for non-hermetic surface mount devices
Classifies how long a plastic package can sit in factory air before moisture it absorbs will crack it during reflow soldering ("popcorning"). MSL 1 is unlimited floor life at 30 C and 85% RH; MSL 3 is 168 hours at 30 C and 60% RH; MSL 6 must be baked before every use.
In practice. The MSL rating is printed on every reel label and drives the dry-pack and handling cost of a package. Mould compound and substrate choices move it.
Also written as moisture sensitivity level, MSL 1, MSL 3, popcorning
Official source IPC/JEDEC J-STD-020↗
On the map Moulding Compound, Moulding, Package Substrates, Tape and Reel
See also J-STD-033, JESD22 test methods
IPC/JEDEC
Handling, packing, shipping and use of moisture/reflow sensitive surface mount devices
How moisture-sensitive parts are dried, sealed with desiccant and a humidity indicator card in a barrier bag, stored, and re-baked if the floor life is exceeded.
Also written as dry pack, moisture barrier bag, HIC, humidity indicator card, bake
Official source IPC/JEDEC J-STD-033↗
On the map Tape and Reel, HAZMAT Logistics
See also J-STD-020 and MSL
Automotive Electronics Council
Failure mechanism based stress test qualification for integrated circuits
The automotive IC qualification. Parts are qualified to an ambient temperature grade: Grade 0 (-40 to +150 C), Grade 1 (-40 to +125 C), Grade 2 (-40 to +105 C) or Grade 3 (-40 to +85 C). The test flow is harsher and larger than JESD47.
In practice. AEC does not certify anything. "AEC-Q100 qualified" is a claim by the chip maker backed by its own test data, which an automotive customer will ask to see. The OSAT and its materials are part of what was qualified, so changing either triggers requalification.
Also written as automotive grade, Grade 0, Grade 1, automotive qualified
Official source AEC qualification documents (Q100 Rev J1 and family)↗
On the map Qualification, Burn-In, Final Test
See also AEC-Q101 to Q104, AEC-Q006, IATF 16949, JESD47
Automotive Electronics Council
Sister qualifications to AEC-Q100 for other device types: Q101 discrete semiconductors (MOSFETs, IGBTs, diodes), Q102 optoelectronics, Q103 MEMS sensors and Q104 multichip modules.
In practice. Q101 is the gate for SiC and GaN power devices going into EVs, the most active compound-semiconductor market.
Also written as AEC-Q101, AEC-Q102, AEC-Q103, AEC-Q104
Official source AEC qualification documents (Q100 Rev J1 and family)↗
On the map Qualification, SiC Substrates, GaN Substrates, SiP Assembly
See also AEC-Q100, AEC-Q200
Automotive Electronics Council
Stress test qualification for passive components: resistors, capacitors, inductors, crystals.
Official source AEC qualification documents (Q100 Rev J1 and family)↗
See also AEC-Q101 to Q104
Automotive Electronics Council
Additional qualification requirements for automotive parts that use copper instead of gold bonding wire. Copper is cheaper but corrodes and cracks differently, so the stress tests run longer.
Also written as copper wire qualification
Official source AEC qualification documents (Q100 Rev J1 and family)↗
On the map Wire Bonding, Bonding Wire
See also AEC-Q100
Industry practice (JESD85 for FIT)
The numbers behind quality claims. Cpk measures how far a process sits inside its specification limits; automotive customers usually ask for 1.33 or 1.67. DPPM is defective parts per million shipped. FIT is failures per billion device-hours, the unit of a field failure rate.
In practice. Automotive chip customers target single-digit DPPM or lower. A supplier who can show Cpk data per lot is easier to qualify than one with only pass/fail records.
Also written as process capability, defective parts per million, failures in time, zero defect, MTTF, JESD85
Official source JEDEC JESD85 (FIT calculation)↗ · AEC qualification documents (Q100 Rev J1 and family)↗
On the map Qualification, Final Test, Metrology
See also AIAG core tools
ESDA/JEDEC
How much electrostatic discharge a device survives. Human Body Model (ANSI/ESDA/JEDEC JS-001) simulates a person touching a pin; Charged Device Model (JS-002) simulates the part itself discharging to a tool. Ratings go on the datasheet.
Also written as JS-001, JS-002, human body model, charged device model
Official source ANSI/ESDA/JEDEC JS-001 (HBM)↗ · ANSI/ESDA/JEDEC JS-002 (CDM)↗
On the map Final Test, Failure Analysis
See also ANSI/ESD S20.20
US Department of Defense (DLA)
Test method standard, microcircuits
The US military test methods for microcircuits, still the reference vocabulary for hi-rel and space parts worldwide: temperature cycling (Method 1010), burn-in (Method 1015), hermeticity, radiography and many more.
In practice. Indian defence and space procurement specifications commonly cite 883 screening methods even where the parts are not US-military.
Also written as Method 1010, Method 1015
Official source DLA: MIL-STD-883↗
On the map Burn-In, Failure Analysis
See also MIL-PRF-38535 (QML), AS9100
US Department of Defense (DLA Land and Maritime)
Qualifies a whole manufacturing line, not a single part, for military (Class Q) and space (Class V) microcircuits: the Qualified Manufacturers List. MIL-PRF-19500 does the same for discrete devices with JAN, JANTX, JANTXV and JANS levels.
Also written as QML, Class Q, Class V, MIL-PRF-19500, JANTX, JANS
Official source DLA: MIL-PRF-38535 QML listing↗ · DLA: MIL-PRF-19500↗
See also MIL-STD-883, AS9100
JEDEC
The family of standards for measuring package thermal resistance (junction-to-ambient, junction-to-case) with defined test boards and conditions, so datasheet numbers are comparable.
Also written as theta-JA, junction-to-ambient, thermal resistance
Official source JEDEC JESD51↗
On the map Thermal Materials, Package Design
JEDEC
The interface definitions that let any memory maker's DRAM work with any processor: JESD79 (DDR, with JESD79-5 for DDR5), JESD209 (LPDDR for phones) and JESD235 / JESD238 (High Bandwidth Memory, stacked beside AI accelerators).
In practice. Memory controller and PHY IP is licensed by compliance to these specifications. HBM is also why 2.5D interposer and hybrid-bonding capacity is scarce.
Also written as JESD79, DDR5, JESD209, LPDDR5, JESD235, HBM, JESD238, HBM3
Official source JEDEC: DDR SDRAM and HBM standards↗ · JEDEC: LPDDR standards↗
On the map Interface PHY IP, 2.5D Packaging, 3D Stacking
JEDEC
JEDEC's registry of standard package outlines (dimensions, pitch, tolerances) for QFN, BGA, SOIC and others. A package that follows a registered outline fits standard sockets, trays and board footprints.
Also written as MO outline, JEDEC outline, package drawing
Official source JEDEC JEP95↗
On the map Leadframes, Test Sockets, Package Design
See also IPC-7351 and IPC-2221
Industry practice
A bare die tested thoroughly enough at wafer level to be trusted without packaging it first. The economics of chiplets and stacked memory depend on it: one bad die in a six-die package scraps five good ones.
Official source An industry term with no single governing standard; each supplier and customer agrees its own test coverage.
On the map Wafer Probe, 2.5D Packaging, 3D Stacking
See also UCIe